1. Field of the Invention
This invention relates generally to digital level detecting circuits and particularly to a digital level detecting circuit for use in controlling the amplitude of a digitized audio signal.
2. Description of the Prior Art
In the audio signal system of an 8-mm VTR (video tape recorder), an electronic still camera and so on, in order to obtain a sufficient dynamic range during recording, the level of the audio signal is compressed according to a predetermined characteristic and is then recorded. During reproduction, the level of the reproduced audio signal is expanded according to a characteristic which is complementary to that used during the recording mode so as to reproduce the original audio signal.
Further, in an 8-mm VTR, the audio signal is converted to a PCM (pulse-code-modulated) audio signal before being recorded. In an electronic still camera, during recording, the audio signal is converted from an analog signal to a digital signal and is then timebase-compressed.
There has been proposed in the prior art a level compressing circuit for compressing the level of an audio signal such as shown in FIG. 1.
FIG. 1 shows an analog audio signal Sa which is supplied through an input terminal 1 to an operational amplifier 2. A variable attenuator (multiplier circuit) 3 is inserted into the negative feedback path of operational amplifier 2. The amount of attenuation of the attenuator 3 is controlled so that an audio signal Sc which has a level which is compressed will be derived from the operational amplifier 2.
Then, the audio signal Sc is supplied to an A/D (analog-to-digital) converter 4 in which it is converted to a digital signal Sd which has a predetermined number of bits (for example, 10 bits). The digital signal Sd is supplied to an output terminal 5. The digital signal Sd is also supplied to a digital level detecting circuit 6 which produces a detected signal V(t) having a level determined by the digital signal Sd (the level of the analog signal after the digital signal Sd has been converted to an analog signal) and which is in the form of a digital signal. The signal V(t) is supplied as the control signal for the attenuator 3.
The signal Sd developed at the output terminal 5 is the digital signal which results from level-compressing and A/D-converting the audio signal Sa.
FIGS. 2A and 2B illustrate examples of an attack response characteristic, a hold response characteristic and a recovery response characteristic for the signal Sd, respectively. In FIGS. 2A and 2B, these response characteristics are illustrated in the form of analog signals.
FIG. 2A illustrates the attack response characteristic. When the level of the signal Sd increases stepwise from a value a to a value b at a time, t=0, the attack response characteristic of the signal (voltage) V(t) is expressed by: EQU V(t)={[b.sup.N -a.sup.N ][1-exp (-t/T]+a.sup.N }.sup.1/N 1
where N and T are constants, respectively.
FIG. 2B illustrates the hold response characteristic and the recovery response characteristic for the signal Sd. When the level of the signal Sd is lowered stepwise from a value a to a value b at a time t=0, during the period of t.ltoreq.t.sub.H, the hold response characteristic of the signal V(t) is expressed by: EQU V(t)=a 2
and, the recovery response characteristic for the period t.gtoreq.t.sub.H is expressed by: EQU V(t)=(b-a) exp [-(t-t.sub.H)/T.sub.R ]+a 3
where t.sub.H and T.sub.R are constants, respectively.
The reason that the signal V(t) has the hold response characteristic and the recovery response characteristic described above is so as to avoid a problem which occurs when the frequency of the signal Sa is low such that the ripple component of the signal V(t) is increased and the signal Sd is modulated with the results that distortion of the low frequency band is increased.
As will be clear from FIG. 2A, in the attack response characteristic, a voltage Vi (=V(i)) at a desired time t=i is provided by adding a voltage V.sub.i-1 (=V (i-1)) at a sampling time t=i-1 which is the time just before the time t=i with a difference of .DELTA.V as shown. The difference .DELTA.V is obtained using an attack response coefficient that is determined by the ratio between the voltage V.sub.i-1 and the absolute value .vertline.Sd.vertline. of the signal Sd. Thus, if the initial value is taken as the value a and this value a is sequentially added to the difference of every sampling period, it is possible to obtain the voltage V(t) at time t. Further, the hold response characteristic is flat as indicated by Eq. (2) and the recovery response characteristic results from adding the value a to the discharge curve (exponential function characteristic) of a capacitor. Thus, if the time base is expressed by a recurrence formula in a discrete manner, Eq. (3) can be rewritten as: EQU V(t)=[.vertline.Sd.vertline.-V (t-1)]k+a (4)
In other words, the voltage V(t) can be obtained such that the value a is taken as the initial value and the value which results from multiplying a constant value k by the difference between the voltage .vertline.Sd.vertline. of the present time t=i and the voltage V.sub.i-1 at the immediately preceding sampling time t=i-1, is repeatedly added to the value a.
Thus the digital level detecting circuit 6 having the desired response characteristics described above can be constructed as shown in FIG. 3.
Referring to FIG. 3, the digital signal Sd is supplied through an input terminal 11 to an absolute value detecting circuit 12 in which it is converted to a signal .vertline.Sd.vertline. which indicates the absolute value .vertline.Sd.vertline. of the signal Sd at the present time t=i. The signal .vertline.Sd.vertline. is supplied to a divider circuit 13 and the divider circuit 13 is supplied the signal V.sub.i 1 (=V (i-1)) at the sampling time t=i-1 which is just before the present time t=i from a latch circuit 18 which will be described later. The divider circuit 13 accomplishes the division of V.sub.i-1 / .vertline.Sd.vertline. by repeating the subtraction of (V.sub.i-1/ .vertline.Sd.vertline.) and the bit-shifting of the signal V.sub.i-1. In the first division, when the first subtraction of (V.sub.i-1 -.vertline.Sd.vertline.) is carried out, as will be clear from FIGS. 2A and 2B, upon attack response, V.sub.i-1 -.vertline.Sd.vertline.&lt;0 is established, and upon hold and recovery response, V.sub.i-1 - .vertline.Sd.vertline..gtoreq.0 is established so that the MSB (most significant bit or code bit) of the (V.sub.i-1 -.vertline.Sd.vertline.) after the first subtraction becomes "1" upon attack response and "0" upon hold and recovery response operations. Therefore, this most significant bit is supplied through a latch circuit 31 to a switching circuit 32 as its control signal.
Upon attack response, the divided signal V.sub.i-1 / .vertline.Sd.vertline. from the divider circuit 13 is supplied to an address signal generating circuit 14 which generates an address signal corresponding to each time from the ratio of V.sub.i-1 / .vertline.Sd.vertline.. This address signal is supplied to a ROM (read only memory) 15 which derives a value (coefficient) K.sub.0 which results from expressing the difference amount .DELTA.V (=V.sub.i -V.sub.i-1) between each time as a percentage. This value k.sub.0 is supplied to a multiplying circuit 16 and the signal .vertline.Sd.vertline. is supplied from the detecting circuit 12 to the multiplying circuit 16 and the signal .vertline.Sd.vertline. is multiplied by the value k.sub.0 to thereby contain the difference amount .DELTA.V at each time increment.
Upon attack response, since the switching circuit 32 is connected in the manner illustrated in FIG. 3, the difference .DELTA.V from the multiplying circuit 16 is supplied through the switching circuit 32 to an adding circuit 17 and also the signal V.sub.i-1 from the latch circuit 18 is supplied to the adding circuit 17. Accordingly, in the adding circuit 17, the difference .DELTA.V is added to the signal V.sub.i-1 to thereby form the signal V.sub.i at the present time. Then, this signal V.sub.i is delivered through the latch circuit 18 to an output terminal 19 so that this signal V.sub.i has the attack response characteristic shown in FIG. 2A.
Upon hold response and recovery response, the most significant bit "0" is generated from the divider circuit 13 as described above. This most significant bit "0" is supplied through the latch circuit 31 to a timer retriggerable counter 21 as its count-clear and count-start signal (count-enable signal), whereby the counter 21 starts counting a clock (not shown) at the time t=0 from the count value "0". Then, the output of the counter 21 is supplied to a ROM 22 as an address signal and a value "0" is derived from the ROM 22 during the period of t.ltoreq.t.sub.H, and a constant value k is derived from the ROM 22 during the period of t&gt;t.sub.H. This value 0 or k is supplied to a multiplying circuit 23.
Also, the signal .vertline.Sd.vertline. from the detecting circuit 12 is supplied to a subtracting circuit 24 and the signal V.sub.i-1 from the latch circuit 18 is supplied to the subtracting circuit 24 which derives a difference .DELTA.V (=.vertline.Sd.vertline.-V.sub.i-1). This difference .DELTA.V is supplied to the multiplying circuit 23 and is multiplied by the value 0 or k. In this case, the difference .DELTA.V is generated at every constant sampling period as shown in FIG. 2B and the recovery response characteristic is provided, as shown in Eq. (3), by adding the value a to a simple exponential function characteristic. Thus, the multiplied output of the difference amount V by the value 0 or k indicates the decreased amount (changed amount) of the signal V(t) at the hold response period (t.ltoreq.t.sub.H) and the recovery response period (t.gtoreq.t.sub.H).
At that time, since the switching circuit 32 is in the state opposite to that illustrated in FIG. 3, the multiplied output of the multiplying circuit 23 is supplied through the switching circuit 32 to the adding circuit 17. Thus, the adding circuit 17 delivers the signal V.sub.i having the hold response characteristic and the recovery response characteristic shown in FIG. 2B. Then, this signal V.sub.i is delivered to the terminal 19.
With the detecting circuit 6, as described above, it is possible to obtain the output control signal V(t) having the attack response characteristic, the hold response characteristic and the recovery response characteristic shown by the Eqs. (1) to (3).
The above mentioned attack response coefficient A(t) is calculated relative to the address p of the ROM 15 as follows. As shown in FIG. 4, a unit step signal is supplied to the detecting circuit 6 as the input signal Sd and the theoretical attack response characteristic (shown by Eq. (1)) of the detecting circuit 6 is used. Then, if a time t which establishes relative to the address p of the ROM 15 the following equation: EQU V(t)=p/2.sup.n
where 2.sup.n is the address space of the ROM 15 taken at time t.sub.1 and the signal V(t) at the next sampling time t.sub.2 (=t.sub.1 +Ts where Ts is the sampling cycle), from time t.sub.1 is expressed by the following equality: EQU V(t.sub.2)=q
the data at the p address of the ROM 15, that is, the attack response coefficient A(p) at the p address of the ROM 15 becomes: EQU A(p)=q-P/2.sup.n ( 5) EQU 0.ltoreq.P&lt;2.sup.n
and this attack response coefficient A(p) becomes as shown by a curve .circle.1 in the graph of FIG. 6. In this case, since the abscissa in FIG. 6, that is, the address p of the ROM 15 is changed with the time t by the address signal generating circuit 14, the abscissa can be considered as the time axis.
In the practical digital level detecting circuit 6, however, it has been proved that when the attack response coefficient A(p) is the theoretical value expressed by the Eq. (5), a problem arises.
Specifically, in the above mentioned level comprising circuit, if there is no delay in the signal processing accomplished by the A/D converter 4 and the like, the waveforms of the respective signals during attach response mode become as shown in FIG. 7A where the digital signal is A/D-converted and is indicated in a waveform for the analog signal. This is done in the same way as described above and does not cause particular problems.
However, in practice, since there is a delay in the signal processing accomplished by the A/D converter 4 and the like, if such play is taken into consideration, the equivalent circuit for the level compressing circuit becomes as shown in FIG. 5. In FIG. 5, a delay element 7 typically represents the delay of the propagation period of the main signal line and this is equal to the delay time of about the several sampling periods.
As a result, upon the attack response in the practical level compressing circuit, the signals Sd and V(t) are delayed relative to the change of the signal Sa as shown in FIG. 7B with the results that the signal Sd falls down more rapidly, that is, the attack response becomes rapid.
In this case, when the duration of the attack response is selected to be long in advance or the sampling frequency relative to the signal Sa is selected to be sufficiently high, the delay by the delay element 7 is small so that the ratio in which the attack response becomes rapid (ratio between the period in which the attack response becomes rapid and the normal attack response period) is small so that this does not cause a serious problem.
However, when the period of the attack response is selected to be short and is selected to be about twice the over-sampling period such as used in the 8-mm VTR, the electronic still camera and so on, the ratio in which the attack response becomes rapid becomes large, which cannot be neglected.
Further, in the above mentioned level detecting circuit 6, since the signal Sd is the discrete signal from a time standpoint, the attack response characteristic of the signal V(t) is scattered by the phase of the sampling time relative to the signal Sa (Sc).
FIGS. 8A and 8B illustrate the signals Sd and V(t) in the form of an analog signal. If the signal Sd is a continuous signal from a time standpoint and is changed as shown by the broken line, the practical signal which is discrete from a time standpoint is obtained by every sampling instance so that it is distributed as shown by the marks .circle. in FIGS. 8A and 8B. FIGS. 8A and 8B illustrate the condition where the phase at the sampling time for the signal Sd is different.
Since the attack response coefficient A(p) is large near the start time (t.congruent.0) of the attack response, as shown by solid lines in FIGS. 8A and 8B, the rise of the signal V(t) becomes different and largely depends on the sampling times of the signal Sd. Then, since the sampling time for the signal Sd is different dependent on the signal Sd, the attack response characteristic is scattered dependent on the signal Sd.
With respect to the hold response characteristic, as shown by the Eq. (2), it is expressed by the following equation during the period of 0.ltoreq.t.ltoreq.t.sub.H EQU V(t)=a
Thus, the level at the time, t=0 is completely held and this is the ideal hold response characteristic.
However, in practice, since the signal Sd is discrete from a time standpoint, an error will occur in the signal V(t).
FIG. 9 shows the signals Sd and V(t) in the form of an analog signal. If the signal Sd is continuous from a time standpoint and is changed as shown by the broken line in the Figure, the practical signal Sd, which is discrete from a time standpoint, is obtained at every sample time and hence is distributed as shown by marks .circle. in FIG. 9.
If the signal Sd provided at a certain time t=t.sub.1 is a data which results from sampling the peak value, the signal Sd and the sampling frequency are not synchronized with each other so that the signal Sd at this time t.sub.1 becomes the last maximum value and the succeeding signal Sd becomes a smaller value than that of the signal at the time t.sub.1.
Accordingly, in the above mentioned digital level detecting circuit 6, the signal V(t) is changed as shown by marks X, that is, V.sub.i-1 .gtoreq..vertline.Sd.vertline. is established from the time t.sub.1 so that the most significant bit from the divider circuit 13 becomes "0" from the time t.sub.1. As a result, the signal V(t) is held from the time, t=t.sub.1. At a time t.sub.9 after the time t.sub.1 by a period t.sub.H occurs, the detecting circuit 6 is set to the recovery response operation mode.
Since the time t.sub.1 at which the signal Sd becomes the data which results from sampling the peak value is changed in association with the sampling operation of the signal Sd, also the position of the hold response operation period t.sub.H is changed. As a result, the holding time (for example, the period from the time t=0 to a time at which the level of the signal V(t) is lowered by 2 dB) is considerably scattered from 0 (time at which the time t=0 and a time t.sub.9 coincide with each other) at minimum to a set value t.sub.H (time at which the time t=0 and t.sub.1 coincide substantially) at maximum.
In the 8-mm VTR, for example, it is assumed that the signal processing of the PCM audio signal is carried out by the level compressing and that the output control signal V(t) is generated in analog fashion. Accordingly, although the signal V(t) is changed as shown by a solid line in FIG. 10, the signal V(t) is changed in the above mentioned detecting circuit 6 as shown by a broken line and the difference therebetween (the hatched portion) causes a problem from an auditory standpoint.